To address the increased noise sensitivity of PAM-4 signaling, PCIe 6.0 introduces Forward Error Correction (FEC).
In previous PCIe generations, errors were handled primarily by the data link layer through retry mechanisms (LCRC). If a packet was corrupted, the receiver asked for it to be sent again. At 64 GT/s, retransmitting data would result in significant latency penalties. pci express base specification revision 60 pdf
PCIe 6.0 uses a Lightweight FEC (L-FEC) mechanism combined with a strong Cyclic Redundancy Check (CRC). To address the increased noise sensitivity of PAM-4
AI training clusters rely on massive data movement between GPUs, TPUs, and HBMs (High Bandwidth Memory). PCIe 6.0 x16 provides ~256 GB/s, allowing larger models to be trained faster without bottlenecks. If you are downloading the PCI Express Base
64 GT/s is an RF nightmare. The PCI Express Base Specification Revision 6.0 PDF contains the specific insertion loss, return loss, and crosstalk budgets. It dictates things like via stub length and material selection (low-loss laminates like Megtron 6).
Because PAM4 is inherently noisier, PCIe 6.0 introduces low-latency FEC as a mandatory feature.
If you are downloading the PCI Express Base Specification Revision 6.0 PDF to understand reliability, focus on Chapter 8 (Physical Layer Logical Sub-block) .