This is the most variable part of the AM4 pin layout. The CPU socket provides the "General Purpose" PCIe lanes.

For context, here is how the AM4 pin layout compares to modern sockets:

| Feature | AM4 (PGA) | AM5 (LGA) | Intel LGA 1700 | | :--- | :--- | :--- | :--- | | Pin/Contact Count | 1,331 pins | 1,718 contacts | 1,700 contacts | | Mechanism | Pins on CPU | Pins in socket | Pins in socket | | Die/Pin Density | Lower (1.0mm pitch) | Higher (0.8mm pitch) | Highest (variable) | | Power Delivery | Mixed core/SOC | Dedicated power vs. I/O | Separate Vcore/VCCGT | | PCIe Support | Up to Gen 4 (5 with X570S) | Gen 5 | Gen 5 | | Common Failure | Bent CPU pins | Bent socket pins | Bent socket pins |

Key Takeaway: AM4's PGA design shifts the risk to the CPU (cheaper to replace) whereas AM5/LGA shifts risk to the motherboard (more expensive to repair).

Tiny pins hidden in the corners.

Unlike older architectures where the memory controller was on the motherboard chipset (Northbridge), the memory controller on AM4 is inside the CPU. The pin layout provides the direct path for the Infinity Fabric—the high-speed interconnect that links the Core Complexes (CCX) to the I/O die and memory controller.

The pins connecting the CPU to the motherboard’s chipset (FCH – Fusion Controller Hub) include: