8bit Multiplier Verilog Code Github -

///////////////////////////////////////////////////////////////////////////////
// Testbench for 8-bit Multiplier
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module tb_eight_bit_multiplier();
// Test vectors
reg [7:0] a, b;
wire [15:0] product;
// Expected results for verification
reg [15:0] expected;
integer error_count;
integer i, j;
// Instantiate the multiplier
eight_bit_multiplier uut (
    .a(a),
    .b(b),
    .product(product)
);
// Test all possible combinations (optional - exhaustive test)
// For 8-bit, exhaustive would be 65536 tests - can run subset
initial begin
    $display("=========================================");
    $display("8-bit Multiplier Testbench");
    $display("=========================================");
error_count = 0;
// Test 1: Basic multiplication
    $display("\nTest 1: Basic Multiplications");
    a = 8'd10; b = 8'd5;
    #10;
    expected = 16'd50;
    check_result();
a = 8'd255; b = 8'd255;
    #10;
    expected = 16'd65025;
    check_result();
a = 8'd0; b = 8'd100;
    #10;
    expected = 16'd0;
    check_result();
// Test 2: Random pattern
    $display("\nTest 2: Random Multiplications");
    for (i = 0; i < 20; i = i + 1) begin
        a = $random % 256;
        b = $random % 256;
        expected = a * b;
        #10;
        check_result();
    end
// Test 3: Boundary conditions
    $display("\nTest 3: Boundary Tests");
    a = 8'd1; b = 8'd1;
    #10;
    expected = 16'd1;
    check_result();
a = 8'd128; b = 8'd2;
    #10;
    expected = 16'd256;
    check_result();
a = 8'd255; b = 8'd1;
    #10;
    expected = 16'd255;
    check_result();
// Test 4: Corner cases
    $display("\nTest 4: Corner Cases");
    a = 8'd255; b = 8'd0;
    #10;
    expected = 16'd0;
    check_result();
a = 8'd0; b = 8'd0;
    #10;
    expected = 16'd0;
    check_result();
// Summary
    $display("\n=========================================");
    if (error_count == 0)
        $display("TEST PASSED! No errors found.");
    else
        $display("TEST FAILED! %0d errors detected.", error_count);
    $display("=========================================");
$finish;
end
task check_result;
    begin
        if (product !== expected) begin
            $display("ERROR: %0d * %0d = %0d (expected %0d)", 
                     a, b, product, expected);
            error_count = error_count + 1;
        end
        else begin
            $display("OK: %0d * %0d = %0d", a, b, product);
        end
    end
endtask
// Monitor signals
initial begin
    $monitor("Time = %0t, a = %0d, b = %0d, product = %0d", 
             $time, a, b, product);
end

endmodule

Booth multiplication reduces the number of partial products by encoding overlapping groups of bits. For an 8-bit multiplier, radix-4 (modified Booth) reduces 8 partial products to 4 or 5. 8bit multiplier verilog code github

module booth_multiplier_8bit (
    input signed [7:0] a, b,   // signed 8-bit inputs
    output signed [15:0] product
);
    reg signed [15:0] pp [0:3];
    integer i;
always @(*) begin
    // Radix-4 Booth encoding of B
    // Simplified example: actual impl requires recoding logic
    for (i = 0; i < 4; i = i + 1) begin
        case (b[2*i+1], b[2*i], b[2*i-1])
            // ... booth encoding cases
            default: pp[i] = 16'sb0;
        endcase
    end
    product = pp[0] + pp[1] + pp[2] + pp[3];
end

endmodule

Why use Booth?

Hardware cost: Moderate — requires encoder, muxes, and an adder tree. endmodule

Resource Utilization:
- LUTs: 125 (Wallace Tree)
- FFs: 32
- I/O: 32
- Maximum Frequency: 125 MHz (Wallace Tree)
- Worst Negative Slack: 0.24 ns